With modem manufacturing techniques, the yield of digital CMOS or memory circuits is primarily limited by random defects that result from random effects such as dust particles or other materials floating in the air, a person coughing or sneezing, etc. Non-random (systematic) defects that result from problems with the manufacturing process and are reproduced regularly on successive ICs, as well as parametric defects in which a part may not quite meet specifications but is still functional, should be reduced or eliminated through rapid learning techniques during the course of manufacturing products in large volumes.
IC chips are fabricated as separate dies on semiconductor wafers. Each die is probed for testing, with failing dies marked with an ink spot. The passing dies are taken from the wafer and assembled into packaged parts, which are again tested. The patterns of good and failing chips at either a wafer or a packaged part level have been used to identify underlying problems in the manufacturing process. This has involved generating a two-dimensional wafer pattern map upon which the defective chips are noted, overlying the wafer defect maps on wafer “signature” maps which display typical defect patterns for various manufacturing line problems, and manually comparing the two in an effort to establish correlation. The identification of statistical trends and development of correlation models has also been used for fault diagnosis; see Kibarian and Strojwas, “Using Spatial Information To Analyze Correlation Between Test Structure Data”, IEEE Transactions on Semiconductor Manufacturing, Vol. 4, No. 3, August 1991. However, the graphical analysis of two-dimensional wafer patterns is an interactive and time consuming process and not practical for application in a real time manufacturing flow.
Another technique that has been used to determine the systematic versus random components of yield loss involves “windowing” on a wafer map. This technique is described, for example, in Stapper et al., “Integrated Circuit Yield Statistics”, Proceedings of the IEEE, Vol 71, No 4, April 1983. It allows the yield to be determined as a function of a “window” of increasing size that is moved around the wafer map. The window is increased from a single die size to two dies, three dies, four dies, and further multiples. Since the likelihood of a defect being included within a particular window area increases as the size of the window become greater, the yield experiences a corresponding reduction. The yields for different window sizes are plotted on the Y-axis of a logarithmic scale against the window area, which is plotted on the X-axis. The resulting curves are extended to intercept the Y-axis, at which the window size is a theoretical zero. The point at which the Y-axis is intercepted is referred to as Yo, and is taken to represent the portion of the total defects attributable to non-random defects. While this technique provides an approximation of the random versus non-random components of defects that effect wafer yield, it is laborious, time consuming, and not particularly accurate.